Preface

The recent close of the OCP APAC 2025 conference has cemented the industry’s commitment to advancing in multiple directions, including CPO technology. TSMC, in response to demands from major AI chip clients, plans to commence mass production of co-packaged optics (CPO) next year. This initiative aims to meet the soaring demands for data transmission speed and energy efficiency fueled by the dramatic growth in AI chip computational power.

Lazy bag

TSMC's move into CPO will drive technological innovation, focusing on wafer testing, fiber optic array units, and high-speed optical packaging. Industry players are expected to benefit significantly.

Main Body

TSMC is leading the charge in the development of CPO technology by integrating cutting-edge innovations across three critical segments: wafer and final testing, fiber optic array units (FAU), and high-speed optical packaging and assembly. As these areas evolve, they will likely spearhead new technology development.

Industry experts are optimistic about the mass production of TSMC's new-gen CPO technology, predicting it will spark a wave of growth opportunities across the supply chain. Companies such as FAU provider Xuan Quan (3363-TW), silicon-based microlens supplier Cai Yu (6789-TW), and testing interface and equipment entity Wang Xi (6223-TW) stand to reap benefits.

The essence of CPO lies in shortening the computational unit and optical engine interface, which significantly improves energy efficiency while reducing latency. TSMC’s CPO strategy involves an 'A+B' integration format, employing Chip-on-Wafer (CoW) technology in computational elements and introducing COUPE (Compact Universal Photonic Engine) technology for optical engines. This hybrid integrated packaging enhances performance.

Using its proprietary SoIC technology, TSMC stacks electronic integrated circuits (EIC) with photonic integrated circuits (PIC) to support grating couplers (GC) and edge couplers (EC). These are further combined with silicon-based microlenses, through-silicon vias (TSV), metal reflective layers, and anti-reflection coatings to efficiently manage optical outputs, allowing seamless interaction between FAU and COUPE. The mature GC supply chain ecosystem prioritizes its development as the primary focus.

TSMC, in collaboration with Cai Yu, is further optimizing silicon-based microlenses by directly depositing them on silicon carriers, enhancing the PIC to FAU optical pathway and minimizing beam scattering. Additionally, TSMC collaborates closely with Xuan Quan for custom FAU design and assembly, having already recognized related NRE expenses, with expected contributions to revenues from client mass productions starting next year. Wang Xi leverages its optical and electrical expertise to engage in cooperative testing initiatives with customers.

TSMC plans to adopt the optical engine on substrate (OE on Substrate) solution for its CPO mass production next year and is developing the OE on Interposer architecture to accommodate more advanced optical transmission needs of its clients.

Key Insights Table