Preface

The world of semiconductor packaging is on the brink of a paradigm shift, spearheaded by TSMC's advancements in CoWoS technology. According to the latest forecast by investment firm Bernstein, the burgeoning demand for advanced packaging due to AI chip necessities will catapult TSMC to the forefront of the packaging domain by 2025, with revenues expected to comprise 10% of the company’s total revenue. This milestone anticipates TSMC overtaking ASE, asserting itself as the globe's largest packaging provider. At the recent TSMC 2025 Technology Forum, this revelatory stride in CoWoS technology was unveiled, signaling a revolutionary breakthrough in high-end chip packaging technologies and foreshadowing the onset of fierce cross-industry competition. This article delves into the implications and future of TSMC’s technological advancements in packaging.

Lazy bag

TSMC's CoWoS technology is transforming the packaging industry, as forecasted to reach new heights by 2025. Strategic collaborations and breakthroughs in power efficiency mark the dawn of a new era.

Main Body

TSMC, globally renowned for its cutting-edge semiconductor solutions, is set to usher in a new era with its CoWoS (Chip on Wafer on Substrate) packaging technology. Forecasts from Bernstein's latest analysis suggest that AI-driven demand for advanced packaging will elevate TSMC's contributions to the field, making up 10% of the company's revenue by 2025. This movement is significant, as it positions TSMC to surpass the current leader, ASE, thus emerging as the preeminent entity in the packaging domain.

At TSMC's 2025 Technology Forum, Senior Vice President and Co-Chief Operating Officer, Zhang Xiaoqiang, introduced the next generation CoWoS blueprint. Described previously as resembling a 'pizza structure,' involving GPU, HBM memory, silicon interposer, and substrate, CoWoS is poised to evolve dramatically. The future iterations promise to transcend from a simple interconnect medium to a multifaceted computing core, capable of integrating numerous IC functionalities.

One groundbreaking innovation presented is the Integrated Voltage Regulator (IVR) technology. By embedding power components directly within the chip, this technology notably enhances power efficiency and improves thermal design, paving the way for significant advancements in AI chip applications. As Zhang explained, positioning voltage regulators closer to processors maximizes power regulation efficiency, heralding a 'structural shift' in the industry.

However, this shift evokes concerns similar to past tech industry shake-ups. Tech leader Ian Jan from Kyocera highlights, "TSMC's prowess in advanced processes sets it apart, and its dominance in advanced packaging may soon follow." This strategy mirrors historical occurrences, akin to Apple's strategic moves in developing Wi-Fi, Bluetooth, and power ICs, ultimately reshaping industry landscapes and prompting competitors such as Qualcomm and Broadcom to exit specific markets. Now, with TSMC joining forces with Nvidia, a new wave of competitive restructuring is anticipated.

Nvidia plays a critical role as a strategic partner in this transformation. Its engineers design IVR components on a 16 nm process, embedding these within a 100-micron thick silicon interposer. Despite the immense technical challenges, as even Nvidia's engineers grapple with feasibility, progress marches on.

The extensive power conversions and rectifications within CoWoS generate significant thermal energy. To counter these issues, TSMC is progressing with cooling solutions, including microchannel cooling and liquid cooling systems, likely setting the standard for future AI chips.

Notable attempts, such as the GB200 NVL72 by Nvidia, exemplify these developments, albeit experiencing production delays due to the immature liquid cooling system. Analysts recognize this as part of Nvidia CEO Jensen Huang’s high-risk approach in pursuit of technological breakthroughs.

As Huang propels the supply chain, he aims to introduce a super-efficient AI computer capable of handling 72 GPUs as a singular computing unit.

The quest for energy efficiency in data centers becomes paramount. Zhang highlights energy efficiency as a crucial metric in AI competitiveness. Delta Electronics' Vice President and General Manager, Chen Ying-yuan, notes that Nvidia's next-generation servers may consume up to 1 MW per rack, equating the power consumption of an entire data center to a nuclear power plant’s output.

With the current grid-to-chip power conversion efficiency at merely 87.6%, leaving 12.4% of energy as heat, effective cooling solutions become essential. As such, comprehensive overhauls of power systems in AI data centers, such as the HVDC (High Voltage Direct Current) 800-volt power systems advocated by Nvidia, become imperative.

Delta’s latest technology boosts efficiency within this framework to 92.5%, representing a 5% energy saving and reducing thermal load by 40%.

As TSMC and Nvidia enhance packaging integration, the ripple effect reverberates through the supply chain, prompting shifts such as Infineon’s move towards self-use of high-end power components, indicating intensifying competition.

The integrative strategy underpinned by TSMC's CoWoS technology is reshaping the AI semiconductor industry. This pivotal transition heralds a focal point in the global packaging and power design landscape over the next few years.

Key Insights Table